Scan conversion apparatus

ABSTRACT

The scan conversion apparatus of the present invention comprises a video signal discriminating circuit for discriminating the kind of input video signal based on an interlaced scanning system; a telecine scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system by processing suited for telecine video signal; a scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system suited for signals other than telecine video signal; and a selector which selects and delivers the output from the telecine scan conversion circuit and the output from the scan conversion circuit in accordance with the result of discrimination executed by the video signal discriminating circuit.

THIS APPLICATION IS A U.S. NATIONAL PHASE APPLICATION OF PCTINTERNATIONAL APPLICATION PCT/JP02/11350.

TECHNICAL FIELD

The present invention relates to a scan conversion apparatus for videosignal and a scan converting method, and particularly, to a scanconversion apparatus to be used when there exist both of telecine videosignal, converted from a movie, and other video signals.

BACKGROUND ART

Recently, a television system is becoming larger in size and higher inpicture quality, and a scan converter is developed for convertinginterlaced scan video signals of present broadcast into progressive scanvideo signals to be displayed.

As such a scan converting method, a prior art is described in thefollowing. Input video signal is compared with fields or frames beforeand after the signal, and detected whether it is of moving pictureregion, still picture region, or medium region in the middle of the bothregions, and classified into these three kinds of regions. In the stillpicture region, the input video signal and video signals before andafter the signal are synthesized as odd horizontal scanning lines andeven horizontal scanning lines, thereby executing line interpolation,and then converted into progressive scan video signal. In the movingpicture region, the input video signal and video signals of horizontalscanning lines above and under the signal are used to obtain videosignals of horizontal scanning lines to be interpolated. In the mediumregion, line interpolation is executed by using the fields in front andback, frames in front and back, and video signals of upper and lowerhorizontal scanning lines in accordance with the level of motion. Themethod described here is called a motion detection scan conversion. (Forexample, Japanese Laid-open Patent 20002-95581).

FIG. 12 shows the relations of movie, telecine video signal, and videosignal after scan conversion. Generally, movie 1201 consists of 24frames per second. In the case of a video signal system of which thenumber of frames per second is 30, the number of frames per second invideo signal does not match the number of frames per second in movie1201. Then, movie 1201 is converted into interlaced scanning videosignal apparently same in structure as conventional video signal. Inthis way, movie 1201 is converted into video signal, which is calledtelecine video signal 1203.

Each frame 1207, 1208, 1209 of movie 1201 is, same as common videosignal, converted into the field of odd horizontal scanning line(hereafter referred to as the first TV field) and the field of evenhorizontal scanning line (hereafter referred to as the first TV field)to become telecine video signal 1203. In this case, field 1210 formed offrame 1207 is re-inserted between the two fields formed of frame 1207and the two fields formed of frame 1208. Also, the field formed of frame1209 is re-inserted after the two fields formed of frame 1209. There-inserted fields are called repeat fields. Such conversion is repeatedto obtain telecine video signal 1203. Thus, 4 frames of movie 1201become 5 frames of telecine video signal 1203.

In this way, movie 1201 of 24 frames per second turns into telecinevideo signal 1203 based on an interlaced scanning system of 30 framesper second. The telecine video signal 1203 includes a repeat field inwhich same field is repeated every 5 fields. A method of generating suchtelecine video signal is called 2–3 pull-down.

The pattern of 5-field period peculiar to telecine video signal 1203 iscalled a telecine pattern. The telecine pattern is represented everyfield by telecine pattern number 1202 of P1 to P5 in the order of time.Also, the telecine pattern number of the repeat field described above isdefined as P1, followed by P2 to P5 in order, which is repeated in orderfrom P1 to P5.

Next, a conventional method for converting telecine video signal 1203into progressive scanning video signal is described as an example.

Telecine video signal 1203 is subjected to the following processing inaccordance with telecine pattern number 1202 for the purpose ofexecuting scan conversion.

One-field earlier telecine video signal 1204 corresponds to telecinevideo signal 1203 delayed by one field. Two-field earlier telecine videosignal 1205 corresponds to telecine video signal 1203 delayed by twofields.

For P1 of telecine pattern number 1202, the field 1210 of telecine videosignal 1203 and the field 1211 of one-field earlier telecine videosignal 1204 are used. Since the field 1210 and field 1211 are signalsformed of same frames 1207 of movie 1201, the two fields are synthesizedto obtain the frame 1220 of progressive scanning video signal 1206.Similarly, for P3, field 1214 and field 1215 are used to form frame1222, and for P5, field 1218 and field 1219 are used to form frame 1224.Also, for P2 of telecine pattern number 1202, the field 1212 ofone-field earlier telecine video signal 1204 and the field 1213 oftwo-field earlier telecine video signal 1205 are used. Since the field1212 and field 1213 are signals formed of same frame 1208 of movie 1201,the two fields are synthesized to obtain the frame 1221 of progressivevideo signal 1206. Similarly, for P4, field 1216 and field 1217 are usedto form frame 1223.

In the scan conversion of the above telecine video signal, when a commonvideo signal that moves every field is applied, there is a possibilitythat completely different video signals are combined to form one frame,and it may cause the picture deterioration such as appearance of doublepictures.

Also, when one telecine video signal is followed by the input of anothertelecine video signal, the scan conversion based on the telecine patternnumber of the initial telecine video signal is executed on the followinganother telecine video signal. As a result, picture deterioration takesplace.

FIG. 13 shows how image deterioration takes place under the abovementioned circumstances.

In FIG. 13, movie 1301, telecine pattern number 1302, telecine videosignal 1303, one-field earlier telecine video signal 1304, two-fieldearlier telecine video signal 1305, progressive scanning video signal1306, fields 1310 to 1319, and frames 1320 to 1323 respectivelycorrespond to the movie 1201, telecine pattern number 1202, telecinevideo signal 1203, one-field earlier telecine video signal 1204,two-field earlier telecine video signal 1205, progressive scanning videosignal 1206, fields 1210 to 1219, and frames 1220 to 1223 in FIG. 12,and the detailed description is omitted. Telecine video signal 1303input is converted into progressive scanning. Telecine video signal 1303is a signal formed with the first telecine video signal 1331 and thesecond telecine video signal 1332 changed over at time. 1330 and joinedwith each other. As mentioned in the description of FIG. 12, since theconversion into progressive scanning is executed on the basis oftelecine pattern number 1302, the video picture is normal up to theframe 1323 of progressive scanning video signal 1306. Since the telecinepattern number 1302 at the time 1333 is P5, frame 1324 is formed on thebasis of field 1318 and field 1319. However, after the time 1330, therepeat field 1340 of second telecine video signal 1332 appears at thetelecine number P4. Field 1318 is a field formed of frame 1309 of movie1301, and field 1319 is a field formed of frame 1308 of movie 1301.Accordingly, frame 1324 formed becomes a picture synthesized withdifferent frames of movie 1301. This may cause the deterioration of thepicture.

DISCLOSURE OF THE INVENTION

The scan conversion apparatus comprises a video signal discriminatingcircuit for discriminating the kind of input video signal based on aninterlaced scanning system, a telecine video scan conversion circuit forconverting input video signal into a video signal based on a progressivescanning system by processing suited for telecine video signal, a scanconversion circuit for converting input video signal into a video signalbased on a progressive scanning system by processing suited for signalsother than telecine video signal, and a selector which selects anddelivers the output from the telecine scan conversion circuit and theoutput from the scan conversion circuit according to the result ofdiscrimination executed by the video signal discriminating circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a scan conversion apparatus in thepreferred embodiment 1 of the present invention.

FIG. 2 is a black diagram of a scan conversion apparatus in thepreferred embodiment 2 of the present invention.

FIG. 3 is a block diagram of a scan conversion apparatus in thepreferred embodiment 3 of the present invention.

FIG. 4 is a black diagram of a scan conversion apparatus in thepreferred embodiment 4 of the present invention.

FIG. 5 is a diagram showing the positional relation between pixel andfield used in an interfield difference detection circuit.

FIG. 6 is a diagram showing a part of flow of an interfield differencedetection circuit.

FIG. 7 is a diagram showing the relationship between pixel and fieldused in an interpixel difference computation circuit.

FIG. 8 is a diagram showing the relationship between pixel and fieldused in an interpixel difference computation circuit in the preferredembodiment 5.

FIG. 9 is a diagram showing a part of flow in the preferred embodiment5.

FIG. 10A is a block diagram of a scan conversion apparatus in thepreferred embodiment 6.

FIG. 10B is a diagram showing the relationship between pixel and fieldused in a scan conversion circuit in the preferred embodiment 6.

FIG. 11 is a block diagram showing the configuration of a frame speeddetection circuit in FIG. 10A.

FIG. 12 is a diagram showing the relations between movie and telecinevideo signal, and between telecine video signal and progressive scanningvideo signal.

FIG. 13 is a diagram showing how image deterioration takes place whentelecine video signal is converted into progressive scanning videosignal by a conventional system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the conventional scan conversion described above, the first telecinevideo signal input is followed by the second telecine video signalinput, and in case the second telecine video signal is different fromthe first telecine video signal with respect to telecine pattern number,the generated progressive scanning video signal is accompanied bypicture deterioration.

Also, when conventional scan conversion described above is applied tocommon video signal that moves every field, there is a possibility thatcompletely different images are combined with each other to form a frameof progressive scanning video signal, and it may cause picturedeterioration.

Accordingly, it is necessary to execute scan conversion with greataccuracy without being accompanied by picture deterioration even whentelecine video signal and other common video signal are changed over orthe telecine pattern of telecine video signal is changed.

The present invention provides a scan conversion apparatus whichexecutes scan conversion with great accuracy without being accompaniedby picture deterioration even when telecine video signal and othercommon video signal are changed over or the telecine pattern of telecinevideo signal is changed,

(Preferred Embodiment 1)

FIG. 1 is a block diagram of a scan conversion apparatus in thepreferred embodiment 1 of the present invention. In FIG. 1, video signalis input via video signal input terminal 108. The input video signal isa video signal based on an interlaced scanning system, which is suppliedto scan conversion circuit 102, telecine detection circuit 105, andinterfield difference detection circuit 106. The telecine detectioncircuit 105, interfield difference detection circuit 106, and first ANDcircuit 107 make up video signal discriminating circuit 103.

The scan conversion circuit 102 compares the input video signal withfields or frames before and after the signal in order to detect whetherit is of moving picture region, still picture region, or medium regionbetween moving picture and still picture. In the still picture region,it executes line interpolation by using the information of fields beforeand after the signal, and in the moving picture region, lineinterpolation is executed by using the information of lines above andunder the signal. In the medium region between moving picture and stillpicture, line interpolation is executed by using the information offields before and after, frames before and after, and scanning linesabove and under. In this way, the scan conversion circuit 102 executesso-called motion detecting scan conversion.

The telecine detection circuit 105 compares the input video signal withits one-frame earlier signal in order to detect repeat field. Also, thetelecine detection circuit 105 outputs the telecine pattern number ofthe repeat field, once input to 5 fields, as P1, and the telecinepattern numbers from P1 to P5 in order together with the relevantpictures. If repeat field once exists in 5 fields, it is judged that theinput video signal is a telecine video signal, then 1 is output asdiscrimination signal, and if not, 0 is output.

The telecine scan conversion circuit 101 inserts the one-field earliervideo signal between the scanning lines of the input video signal togenerate progressive scanning video signal when the telecine patternnumbers output from the telecine detection circuit 105 are P1, P3, orP5. Also, when the telecine pattern numbers are P2 or P4, the two-fieldearlier video signal is inserted between the scanning lines of theone-field earlier video signal of the input video signal to generateprogressive scanning video signal.

The interfield difference detection circuit 106 receives the input videosignal, the discrimination signal output from the telecine detectioncircuit 105, and the telecine pattern number. As discrimination signal,when the input is 1, meaning a telecine video signal, the signal isprocessed as followed in accordance with the telecine pattern numbers.When the telecine pattern numbers are P1, P3, or P5, the interfielddifference detection circuit 106 takes the field difference between theinput video signal and the one-field earlier video signal. When thepattern numbers are P2 or P4, the interfield difference detectioncircuit 106 takes the field difference between the one-field earliersignal and the two-field earlier signal from the input signal. In casethe difference is slight, the interfield difference detection circuit106 judges that the two fields correspond to video signal formed of aframe generated from one frame of movie, and then outputs 1 as Flag.Also, if the difference is great, the interfield difference detectioncircuit 106 judges that the two fields do not correspond to a framegenerated from one frame of movie, and then outputs 0 as Flag.

When the input video signal is a telecine video signal, the two fieldscompared with respect to the telecine pattern numbers P1, P3, P5 and P2,P4 must be originally a video signal generated from same frame of movie.However, the great difference means that the telecine pattern numbersoutput from the telecine detection circuit 105 do not match the telecinepattern numbers of the input video signal at present. Accordingly, itmeans that the telecine scan conversion circuit 101 executing the scanconversion under the control of the telecine pattern numbers isexecuting inappropriate scan conversion.

Therefore, when both of the Flag from the interfield differencedetection circuit 106 and the discrimination signal of the telecinedetection circuit 105 are 1, it is judged that the input video signal isa telecine video signal and that the telecine pattern numbers match thetelecine patterns of the input video signal, and then the first ANDcircuit 107 outputs 1. Otherwise, the first AND circuit 107 outputs 0.The first selector 104 outputs the progressive scanning video signalfrom the telecine scan conversion circuit 101 only when 1 is output fromthe first AND circuit 107, and otherwise, the progressive video signalfrom the scan conversion circuit 102 is output.

Thus, even when the telecine pattern numbers output from the telecinedetection circuit 105 are wrong, and the telecine pattern numbers do notmatch the telecine patterns of the video signal, the error can bedetected and it is possible to select the scan conversion system withgreat accuracy.

(Preferred Embodiment 2)

FIG. 2 is a block diagram showing the detail of the interfielddifference detection circuit 106 of FIG. 1 in the preferred embodiment 1of the present invention.

As for the items described in the preferred embodiment 1 and notdescribed in the preferred embodiment 2, the description holds true inthe preferred embodiment 2 as well, and the detailed description isomitted.

In FIG. 2, the interfield difference detection circuit 106 comprisesinterpixel difference computation circuit 201, first register 202, firstcomparator 203, cumulative addition circuit 204, second register 205,and second comparator 206.

The interpixel difference computation circuit 201 takes the differencein luminance signal level between the pixels at same position in twofields of one frame probably generated from same frame of movie. Here,pixels at same position correspond to pixels at the same number ofhorizontal scanning lines counted from the vertical sync signal and atthe same number of pixels counted from the horizontal sync signal.

The first register 202 stores the first threshold value for comparisonwith the differential pixel value of luminance level which is the outputresult of interpixel difference computation circuit 201. The firstcomparator 203 compares the differential pixel value of luminance level,the output result of interpixel difference computation circuit 201, withthe first threshold value. When the output from the interpixeldifference computation circuit 201 is greater than the first thresholdvalue, 1 is output, and otherwise, 0 is output.

The cumulative addition circuit 204 executes cumulative addition for onefield of the output from first comparator 203. The second register 205stores the second threshold value for comparison with the output resultof cumulative addition circuit 204. The second comparator 206 comparesthe output from cumulative addition circuit 204 with the secondthreshold value. When the output from cumulative addition circuit 204 isgreater than the second threshold value, 0 is output, and otherwise, 1is output.

The preferred embodiment 2 is further described by using FIG. 5, FIG. 6,and FIG. 7.

Video signal and telecine pattern numbers output from the telecinedetection circuit 105 are input to the interpixel difference computationcircuit 201. When the telecine pattern numbers are P1, P3, or P5, theinput video signal and one-field earlier video signal are used toexecute the following processing, and in case of P2 or P4, the videosignal one-field earlier and the video signal two-field earlier than theinput video signal are used to execute the following processing.

In FIG. 5, field 501 shows the M-th field, and field 502 shows the(M−1)th field, that is, the field one-field earlier than the field 501.When the telecine pattern numbers output from the telecine detectioncircuit 105 are P1, P3, or P5, the field 501 is the input video signal,and the field 502 is the video signal one-field earlier than the inputvideo signal. When the telecine pattern numbers are P2 or P4, the field501 is the video signal one-field earlier then the input video signal,and the field 502 is the video signal two-field earlier than the inputvideo signal. In field 501, the value of pixel A that is the x-th pixelcounted from the horizontal sync signal on the y-th horizontal scanningline counted from the vertical sync signal is represented by A (x, y).In field 502, the value of pixel B that is the x-th pixel counted fromthe horizontal sync signal on the y-th horizontal scanning line countedfrom the vertical sync signal is represented by B (x, y). The interpixeldifference computation circuit 201 obtains the difference in luminancelevel between A (x, y) and B (x, y) as the output. Incidentally, thisoperation is not executed during the blanking period of the picture.

FIG. 7 shows the relative positions of pixels for difference computationin the interpixel difference computation circuit 201. As describedabove, when the telecine pattern numbers of the telecine video signalare P1, P3, or P5, the field (field 501) of the video signal to be inputand one-field earlier video signal (field 502) are used, and in case ofP2 or P4, the signal (field 501) one-field earlier and the video signal(field 502) two-field earlier against the input video signal are used.In FIG. 7, the field 501 is the first TV field, and the field 502 is thesecond TV field. Pixel 701 and pixel 703 are pixels on the horizontalscanning line of field 501, and pixel 702 and pixel 704 are pixels onthe horizontal scanning line of field 502. Both fields shown herecorrespond to the same frames generated by same frames of movie. Eachpixel shown by a circle corresponds to A (x, y) in FIG. 5, and eachpixel shown by a shaded circle corresponds to B (x, y) in FIG. 5.

FIG. 6 is a flow chart showing the operation of the interpixeldifference computation circuit 201, the first register 202, and thefirst comparator 203 in FIG. 2. In step 601 (Start), the process isstarted, and in step 602, the computation is executed by using A (x, y)and B (x, y). C (x, y) is the value obtained by subtracting B (x, y)from A (x, y). C (x, y) is the computation result output from theinterpixel difference computation circuit 201. Next, in step 603, thedifference between C (x, y) and the first threshold value V stored inthe first register 202 is judged. C (x, y) is compared with the firstthreshold value V. When C (x, y) is equal or greater than the firstthreshold value V, it goes to the step 605, and 1 is output in a sensethat the video contents are different between both fields. And, when C(x, y) is less than the first threshold value V, it goes to the step604, and 0 is output in a sense that there is no difference between bothfields with respect to the video contents.

The cumulative addition circuit 204 executes cumulative addition of theoutput results from the first comparator 203 within the effective periodof the picture, that is, other than the blanking period, and outputs theresult of addition. The second register 205 stores the second thresholdvalue compared with the output result of cumulative addition circuit204. The second comparator 206 outputs 0 when the output result ofcumulative addition circuit 204 is equal or greater than the secondthreshold value, and outputs 1 when the output result of cumulativeaddition circuit 204 is less than the second threshold value. It becomesFlag that is the output from interfield difference detection circuit106. In this way, the difference between fields is detected every pixel,and thereby, the interfield difference detection circuit 106 executesaccurate detection even against very high definition video signals.Also, even in case of video signal with unspecific elements such asnoise added thereto, the detection results hardly influenced by suchunspecific elements can be obtained by comparing the output result ofinterpixel difference computation circuit 201 with the first thresholdvalue to output the result of checking for difference between thepixels.

In the above description, the cumulative addition circuit 204 executesthe addition with respect to all pixels except during the blankingperiod.

However, artificial pictures are sometimes superposed on the videosignal. For example, superimposed dialogue or time is sometimessuperposed. When such signal is superposed, the portion of the pictureis different in property from other portions. If the videodiscrimination circuit 103 executes the video discrimination includingthe superposed portion, there is a possibility that faulty operationtakes place in video discrimination. In order to avoid such problem, thepresent invention can be configured in that the cumulative additioncircuit 204 does not operate on the whole picture but on a limitedregion except the extremity portions and the like of the picture. Inthis way, it is possible to realize more reliable video signaldiscrimination and to obtain a scan conversion apparatus capable offurther reducing the possibility of picture deterioration.

(Preferred Embodiment 3)

Next, FIG. 3 is a block diagram showing a video conversion apparatus inthe preferred embodiment 3 of the present invention. In the figure,those other than the threshold control circuit 301 are same as in FIG.2.

The second threshold value stored in the second register 205 in FIG. 2is a fixed value. However, in FIG. 3, the second threshold value storedin the second register 205 is controlled by the threshold controlcircuit 301.

Video signal including much region of flat pictures such as animation ismentioned as an example. In video signal including much region of flatpictures, there exists much region where the differential pixel valuecalculated by the interpixel difference computation circuit 201 isrelatively small. Consequently, for the differential sum for one fieldobtained by the cumulative addition circuit 204, the sum is relativelysmall, and it is sometimes unable to detect even when there existediting points of telecine video signal and the like.

In order to prevent such faulty operation, the threshold control circuit301 observes the differential sum output from the cumulative additioncircuit 204. For example, the threshold control circuit 301 calculatesthe average of differential sum for 4 fields, excluding the largestvalue from among the five fields, out of the differential sum outputfrom the cumulative addition circuit 204. The second threshold valuestored in the second register 205 is increased or decreased inaccordance with the average value. For example, when the average valueis relatively small, the second threshold value is decreased, and thesecond threshold value is supplied to the comparator 206.

The largest value of the differential sum is excluded from among thefive fields as described above because there is a high possibility thatthe largest field of the differential sum is the editing point of thetelecine video signal.

By using such a configuration, it is possible to precisely detect theediting point even in case of telecine video signal whose differenceoutput from the interpixel difference computation circuit 201 isrelatively small. As a result, a scan conversion apparatus capable ofsuppressing the generation of picture deterioration can be realized.

(Preferred Embodiment 4)

Next, FIG. 4 is a block diagram showing a scan conversion apparatus inthe preferred embodiment 4. In the figure, those other than filtercircuit 401 are same as in FIG. 2. Accordingly, the detailed descriptionof those other than the filter circuit 401 is omitted.

In FIG. 4, the video signal applied to the video signal input terminal108 is supplied to the filter 401 and the scan conversion circuit 102.The filter 401 serves to filter the input video signal with respect tospecific characteristics. The filter 401 is used for avoiding faultyoperation due to undesirable component such as noise included in theinput video signal and for avoiding faulty operation due to carrierchrominance signal component. The filter 401 used for eliminatingundesirable component such as noise included in the input signal is, forexample, a low-pass filter. The filter 401 used for eliminating carrierchrominance signal component is, for example, a band-suppression filter.

Thus, it is possible to reduce faulty operation in the telecinedetection circuit 105 and the interfield difference detection circuit106. Consequently, the quality and reliability of scan conversionapparatus is improved.

(Preferred Embodiment 5)

The preferred embodiment 5 of the present invention will be described byusing FIGS. 7, 8, 9. Incidentally, as for the items described in each ofthe above preferred embodiments and not described in the preferredembodiment 5, the description falls true in the preferred embodiment 5as well, and the detailed description is omitted.

The preferred embodiment 5 refers to a method of computing interpixeldifference, wherein the computation of interpixel difference is executedaccording to the operation different from that of the interpixeldifference computation circuit 201 in the preferred embodiment 2.

In FIG. 7, A (x, y) and B (x, y) are same in the number of horizontalscanning lines from the vertical sync signal respectively, and also samein the number of pixels from the horizontal sync signal. However, evenin case of being formed of same frame of movie, these pixels are not incompletely same position, but there is a difference equivalent to thehorizontal scanning line interval on the progressive scanning videosignal.

Therefore, in the preferred embodiment 5, pixels used for taking thedifference are generated by the method shown in FIG. 8. In FIG. 8, sameas in FIG. 7, field 501 is the first TV field, and field 502 is thesecond TV field. Also, pixel 701 and pixel 703 are pixels on thehorizontal scanning line of field 501, and pixel 702 and pixel 704 arepixels on the horizontal scanning line of field 502.

First, luminance level H (x, y) having a component, H (x, y)=(A (x,y−1)+3×A(x, y))/4, is generated from the luminance level of A (x, y−1)and A (x, y). Also, luminance level J (x, y) having a component, J (x,y)=(3×B (x, y−1)+B (x, y))/4, is generated from the luminance level of B(x, y−1) and B (x, y).

Next, in the flow chart of FIG. 9, the operation of interpixeldifference computation circuit 201, first register 202, and firstcomparator 203 will be described in the following.

In step 901 (Start), the process is started. Subsequently, in step 902,K (x, y) is calculated. The difference between H (x, y) having theluminance level of A (x, y−1) and A (x, y) described in FIG. 8 by aratio of 1 to 3 and J (x, y) having the luminance level of B (x, y−1)and B (x, y) by a ratio of 3 to 1 is K (x, y). Next, it goes to the step903. When K (x, y) is equal or greater than the first threshold value Vstored in the first register 202, it goes to the step 905, and then 1 isoutput, and when K (x, y) is less than the first threshold value V, itgoes to the step 904, and then, 0 is output.

The above process corresponds to such operation that the luminance levelcomponent of pixel to be compared is calculated by a ratio in accordancewith the position of the pixel to generate H (x, y) and J (x, y),thereby generating the luminance level of pixels of same position. Thatis, the pixels shown by circles and the pixels shown by shaded circlesin FIG. 8 are converted into pixels of same vertical position. Pixel 801shown by an triangle is one of the examples. Accordingly, the outputresult from the interpixel difference computation circuit 201 does notinclude the component of luminance level difference due to thedifference in pixel position, and thereby, highly accurate computationresult can be obtained.

As described above, according to the scan conversion apparatus of thepresent invention, even when the input video signal includes both oftelecine video signal and other video signals, or even in case the inputvideo signal has a new telecine pattern as the telecine pattern isinterrupted amidst the telecine video signal, it is possible toaccurately detect whether it is a picture whose one frame is formed ofsame frame of movie by comparing the two fields combined. On the basisof the detection result, the scan conversion method for telecine videosignal and the scan conversion method for other video signals can beaccurately changed over.

Also, in the present invention, it is possible to detect the bordertiming between telecine video signal and other video signal, or theborder timing between telecine video signal and another telecine videosignal in which repeat field exists in timing different from thetelecine video signal. As a result, even when there exist both oftelecine video signal and other video signals, the telecine video signalcan be accurately detected, and it is possible to realize progressivescan conversion without picture deterioration due to wrong selection thescanning line interpolation method.

Also, in the present invention, in the comparison of fields of framegenerated from same frame of movie, pixels in specified pixel positionsare sequentially compared with each other, and the boundary timingbetween telecine video signal and other video signal or between thetelecine video signal and telecine video signal where the repeat fieldexists in different timing from that of the telecine video signal can bedetected according to the result of cumulative addition in one field ofcomparison result. Highly accurate field comparison can be executed bymaking the comparison every pixel also with respect to very fine videosignals. Since the telecine pattern detection of telecine video signalcan be accurately executed, it is possible to execute progressive scanconversion without picture deterioration due to wrong selection of thehorizontal scanning line interpolation method.

Also, in the present invention, in the comparison of fields of framegenerated from same frame of movie, video signals corresponding to sameposition with respect to each field are generated from pixels used forcomparison and pixels therearound so that the pixels used for comparisonare not deflected from each other by ½ of the horizontal scanning lineinterval. The result of comparison of the pixels thus produced isaccumulated in the field, and the telecine video signal and other videosignals are precisely detected according to the result of theaccumulation. Also, the telecine video signal and telecine video signalin which the repeat field exists in timing different from the telecinevideo signal are precisely detected. As a result, the pattern detectionof telecine video signal can be accurately performed, and it is possibleto realize progressive scan conversion without picture deterioration dueto wrong selection of the scanning line interpolation method.

(Preferred Embodiment 6)

FIG. 10A shows a block diagram of a scan conversion apparatus in thepreferred embodiment 6 of the present invention. Also, FIG. 11 is adiagram showing in detail a part of FIG. 10A.

In FIG. 10A, video signal input terminal 108, scan conversion circuit102, video signal discriminating circuit 103, telecine scan conversioncircuit 101, first selector 104, telecine detection circuit 105, andvideo signal output terminal 109 are same as those in FIG. 1, and thedetailed description is omitted.

Video signal is input to the telecine detection circuit 105, and whenthe video signal is a telecine video signal, the telecine detectioncircuit 105 outputs 1 as the discrimination signal, and if not, itoutputs 0 as the discrimination signal. The scan conversion circuit 102is a scan conversion circuit for converting video signal other thantelecine video signal into progressive scanning. The frame speeddetection circuit 1001 detects the frame speed of the input video signalevery pixel. The telecine scan conversion circuit 101 executesprogressive scan conversion suited for telecine video signal. NOTcircuit 1002 executes logical NOT of the output from the frame speeddetection circuit 1001 and supplies it to the second AND circuit 1003.The second AND circuit 1003 obtains the logical product of thediscrimination signal from the telecine detection circuit 105 and theoutput from NOT circuit 1002. The video signal discriminating circuit103 comprises the frame speed detection circuit 1001, telecine detectioncircuit 105, NOT circuit 1002, and second AND circuit 1003. The firstselector 104 is controlled by the output from the second AND circuit1003. The first selector 104 selects the output from telecine scanconversion circuit 101 when the output from the second AND circuit 1003is 1, and the output from scan conversion circuit 102 when the outputfrom the second AND circuit 1003 is 0.

FIG. 11 shows the configuration of frame speed detection circuit 1001 ofFIG. 10A. In FIG. 11, line memory 1106 stores the input video signal forone horizontal scanning period, and delivers the output, in the order ofinput, in timing delayed by constant time from the input of the nexthorizontal sync signal. The delay by constant time is adjusted so thatthe input timing of effective pixels of the next horizontal scanningline is simultaneous with the output timing of effective pixels from theline memory 1106.

Next, multiplier 1108 converts the output video signal from the linememory 1106 into a triplex value. Adder 1110 adds the output videosignal and input video signal from the multiplier 1108. Divider 1112converts the output video signal from the adder 1110 into a quartervalue.

Accordingly, when the pixel value of video signal input through thevideo signal input terminal 108 is Y, and the pixel value of videosignal output from the line memory 1106 is Y1, then the output videosignal Y2 from the divider 1112 can be represented by formula 1.Y 2=(Y+3×Y 1)/4  (Formula 1)

Also, the line memory 1107 stores the input video signal for onehorizontal scanning period, and delivers the output, in the order ofinput, after lapse of constant time from the next horizontal sync signalinput. The delay by constant time is adjusted the same as in theoperation of line memory 1106 so that the input timing of effectivepixels of the next horizontal scanning line is simultaneous with theeffective pixel output from the line memory 1107.

Multiplier 1109 converts the input video signal into a triplex level,and adder 1111 adds the output from the line memory 1107 and the outputfrom the multiplier 1109. Divider 1113 converts the output from theadder 1111 into a quarter level.

Accordingly, when the pixel value of video signal input through thevideo signal input terminal 108 is Y, and the pixel value of videosignal output from the line memory 1107 is Y3, then the output videosignal Y4 from the divider 1113 can be represented by formula 2.Y 4=(3×Y+Y 3)/4  (Formula 2)

The outputs from divider 1112 and divider 1113 are input to the secondselector 1114.

The line memory 1106, line memory 1107, multiplier 1108, multiplier1109, adder 1110, adder 1111, divider 1112, and divider 1113 make up thefirst weighted sum circuit group 1130.

Field detection circuit 1129 outputs 0 when the video signal inputthrough the video signal input terminal 108 is a signal of first TVfield, and outputs 1 when it is second TV field. The output from thefield detection circuit 1129 is input as a selection control signal tothe second selector 1114 and the third selector 1124. The secondselector 1114 supplies the output video signal from the divider 1113,when the input from the field detection circuit 1129 is 0, and theoutput from the divider 1112, when the input from the field detectioncircuit 1129 is 1, respectively to the first subtraction circuit 1125.

Similar processing is also executed on the video signal 1-field delayedby the field memory 1115.

The line memory 1116 and line memory 1106, the line memory 1117 and linememory 1107, the multiplier 1118 and multiplier 1108, the multiplier1119 and multiplier 1109, the adder 1120 and adder 1110, the adder 1121and adder 1111, the divider 1122 and divider 1112, the divider 1123 anddivider 1113, and the selector 1124 and selector 1114 are respectivelyidentical in operation with each other. Also, the line memory 1116, linememory 1117, multiplier 1118, multiplier 1119, adder 1120, adder 1121,divider 1122, and divider 1123 make up the second weighted sum circuitgroup 1130. The third selector 1124 selects the output from divider 1123when the output from field detection circuit 1129 is 1, and the thirdselector 1124 selects the output from divider 1122 when the output fromfield detection circuit 1129 is 0.

The output signals from the second selector 1114 and the third selector1124 are input to the first subtracter 1125, and the first subtracter1125 calculates the differential between the two for each pixel.

As for the pixel selected by the second selector 1114 and the thirdselector 1124 according to the selection control signal from the fielddetection circuit 1129, the phase deflection of horizontal scanning lineof each field that exists because of interlaced scanning video signal iseliminated in the operation of formula 1 and formula 2. As for pixels ofwhich the difference as the operational result of first differencecalculator 1125 are relatively great, it can be judged that they are notthe pixels in a frame formed of same frame of movie.

Here, there is a possibility that noise or video signal varying everyline is sometimes input to the video signal, and it may be output as adifferential signal. Also, the substantial frame speed of telecine videosignal is 24 per second, while the frame speed of common video signal is30 per second. However, even in case of video signal whose frame speedis different from that of telecine video signal, there arises no problemsuch as double line display if it is a still picture.

Accordingly, even in case of pixels of different frame speed, it ispreferable to use the conversion output at the scan conversion circuit102 only against the portion judged to be a moving picture throughmoving picture detection. And, the frame memory 1126 stores one frame ofvideo signal input through the video signal input terminal 108. Thesecond subtracter 1127 calculates the difference between the videosignal input via the video signal input terminal 108 and the videosignal output from the frame memory 1126. When the difference is great,the pixel is judged to be a moving picture pixel.

The third AND circuit 1128 outputs 1 when the pixel is of differentframe speed and is a moving picture pixel, and in other cases, outputs 0as the signal from the frame speed detection circuit 1001.

The NOT circuit 1002 reverses the output from the frame speed detectioncircuit 1001 and supplies it to the second AND circuit 1003. The secondAND circuit 1003 takes the logical product of the output from thetelecine detection circuit 105 and NOT circuit 1002. The first selector104 operates in accordance with the output from the second AND circuit1003. The first selector 104 supplies the output from the telecine scanconversion circuit 101 when the output from the second AND circuit 1003is 1, and the output from the scan conversion circuit 102 when theoutput from the second AND circuit 1003 is 0, respectively to the videosignal output terminal 109.

By using the preferred embodiment 6 described above, even in case ofvideo signal input of which video signal different in frame speed ismultiplexed on telecine-converted video signal, it is possible toprevent picture deterioration such as double picture by selecting a scanconversion method suited for each video signal.

Incidentally, the coefficients of the multipliers and the dividers inthe preferred embodiment 6 are set so as to minimize the memoriesrequired.

Also, FIG. 11 shows a configuration using line memories 1106, 1107,1116, and 1117, but it is also possible to adopt a configuration usingthe line memories 1106 and 1107 or line memories 1116 and 1117 incompatible fashion.

Also, FIG. 11 shows a configuration wherein the first subtractioncircuit 1125 is directly connected to the third AND circuit 1128, andalso the second subtraction circuit 1127 is directly connected to thethird AND circuit 1128. It is also possible to insert a circuit whichoutputs 0 or 1 on the basis of the output value of the first subtractioncircuit 1125 between the first subtraction circuit 1125 and the thirdAND circuit 1128. It is also possible to insert a circuit which outputs0 or 1 on the basis of the output value of the second subtractioncircuit 1127 between the second subtraction circuit 1127 and the thirdAND circuit 1128.

Also, it is possible to omit the NOT circuit 1002 of FIG. 10A, changingthe third AND circuit 1128 to NAND circuit.

(Preferred Embodiment 7)

The preferred embodiment 7 of the present invention will be described inthe following.

In the preferred embodiment 7, the scan conversion circuit 102 in FIG.10A executes adaptive scan conversion.

FIG. 10B is a diagram for describing the adaptive scan conversion,showing continuous three fields. In FIG. 10B, field 1011 is a field (Mfield) input at present, field 1012 is a field ((M−1) field) one-fieldearlier than the field 1011, and field 1013 is a field ((M+1) field)one-field later than the field 1011. The value of pixel A, x-th one fromthe horizontal sync signal, on the y-th horizontal scanning line in thefield 1011 is A (x, y), the value of pixel B1, x-th one from thehorizontal sync signal, on the y-th horizontal scanning line in thefield 1012 is B1 (x, y), the value of pixel B1, x-1st one from thehorizontal sync signal, on the y-1st horizontal scanning line in thefield 1012 is B1 (x1, y1), the value of pixel B2, x-th one from thehorizontal sync signal, on the y-th horizontal scanning line in thefield 1013 is B2 (x, y), and the value of pixel B2, x-2nd one from thehorizontal sync signal, on the y-2nd horizontal scanning line in thefield 1013 is B2 (x2, y2).

The adaptive scan conversion circuit 102 judges which pixels must beused along with the pixel A (x, y) of field 1011 input at present forgenerating progressive scan video signal. When the difference betweenpixel A (x, y) and B1 (x, y) is increased due to motion or the like, asto B1 (x, y) in the field 1012 and pixel in the field 1013, that isdifferent in position from pixel B2 (x, y), pixel being highlycoincidental with pixel A (x, y) is searched for. As a result, pixel B1(x1, y1) existing in the field 1012 and B2 (x2, y2) existing in thefield 1013 are found out. Then, it is converted into progressive scanvideo signal by using pixel A (x, y) and pixel B1 (x1, y1) or pixel B2(x2, y2).

Thus, the adaptive scan converter 102 executes the conversion intoprogressive scan video signal against video signal pixels different inframe speed detected by the frame speed detector 1001 by using highlycorrelated pixels out of the video signal fields input earlier and laterin time. In this way, even when the frame speed is different, scanconversion is executed between highly correlated video signals, therebyrealizing ideal scan conversion.

As described above, according to the scan conversion apparatus of thepresent invention, even when there exist both of telecine video signaland video signal having a frame speed different from that of thetelecine video signal, the method of scan conversion into progressivescanning can be changed over by detecting the frame speed every pixel.As a result, it is possible to execute ideal progressive scan conversionagainst telecine video signal, and scan conversion suited for the videosignal against video signal having a frame speed other than that of thetelecine video signal.

Also, as to video signal pixels of different frame speed, progressivescan conversion of high picture quality can be executed by using highlycorrelated video signals out of the fields earlier and later in time.

Also, even in case of wrong detection of frame speed, it is possible toperform progressive scan conversion hardly accompanied by picturedeterioration.

INDUSTRIAL APPLICABILITY

The video signal detector of the present invention is able to realizescan conversion with high picture quality even when the input videosignal includes both of telecine video signal and other video signal, orthe input video signal has a new telecine pattern as the telecinepattern is interrupted amidst the telecine video signal, or there existboth of telecine video signal and video signal having a frame speedother than that of the telecine video signal.

1. A scan conversion apparatus comprising: a video signal discriminatingcircuit for discriminating kinds of input video signals based on aninterlaced scanning system; a telecine video scan conversion circuit forconverting said input video signal into a video signal based on aprogressive scanning system by processing suited for telecine videosignal; a scan conversion circuit for converting said input video signalinto a video signal based on a progressive scanning system by processingsuited for signals other than telecine video signal; and a firstselector which selects and delivers output from said telecine scanconversion circuit and output from said scan conversion circuit inaccordance with result of discrimination executed by said video signaldiscriminating circuit, wherein said video signal discriminating circuitcomprises: a telecine detection circuit which outputs telecine patternnumber and discrimination signal showing whether the input video signalis a telecine signal or not; an interfield difference detection circuitwhich outputs Flag related to the level of coincidence between fields ofsaid input video signal according to the telecine pattern number; and afirst AND circuit which obtains an output from said video signaldiscriminating circuit by calculating the logical product of thediscrimination signal and the Flag, wherein said telecine scanconversion circuit converts the input video signal into a video signalbased on a progressive scanning system in accordance with the telecinepattern number.
 2. The scan conversion apparatus of claim 1, whereinsaid interfield difference detection circuit comprises: a pixeldifference computation circuit for detecting difference in pixel valuebetween specified adjacent fields in accordance with the telecinepattern number; a first comparator which outputs result of comparisonbetween the difference and first threshold value; a cumulative additioncircuit which accumulates output from the first comparator and outputscumulative value; and a second comparator which outputs the Flag inaccordance with result of comparison between the cumulative value andsecond threshold value.
 3. The scan conversion apparatus of claim 2,wherein the pixel value is the value of a pixel in same position countedin a vertical direction from vertical blanking and in same positioncounted in a horizontal direction from horizontal blanking.
 4. The scanconversion apparatus of claim 2, wherein the pixel value is a valueobtained through weighted operation between pixels respectively locatedin same horizontal position within a field.
 5. The scan conversionapparatus of claim 2, wherein said cumulative addition circuit executescumulative addition only within a specified region of a field.
 6. Thescan conversion apparatus of claim 2, wherein said interfield differencedetection circuit further includes a threshold control circuit, and saidthreshold control circuit controls the second threshold value inaccordance with the amount of a value from which the largest valuewithin one period of the telecine pattern number is excluded in eachfield output from said cumulative addition circuit.
 7. The scanconversion apparatus of claim 1, wherein said video signaldiscriminating circuit further includes a filter, and said filter servesto filter the input video signal, and the output from said filter isinput to at least one of said telecine detection circuit and saidinterfield difference detection circuit.
 8. The scan conversionapparatus of claim 1, wherein said scan conversion circuit generates aprogressive scan video signal with use of said input video signal andhighly correlated video signals in fields before and after the signal.9. The scan conversion apparatus of claim 1, wherein said scanconversion circuit generates a progressive scan video signal with use ofhighly correlated video signals in said input video signal.
 10. A scanconversion apparatus comprising: a video signal discriminating circuitfor discriminating kinds of input video signals based on an interlacedscanning system; a telecine video scan conversion circuit for convertingsaid input video signal into a video signal based on a progressivescanning system by processing suited for telecine video signal; a scanconversion circuit for converting said input video signal into a videosignal based on a progressive scanning system by processing suited forsignals other than telecine video signal; and a first selector whichselects and delivers output from said telecine scan conversion circuitand output from said scan conversion circuit in accordance with resultof discrimination executed by said video signal discriminating circuit,wherein said video signal discriminating circuit comprises: a telecinedetection circuit which outputs a discrimination signal showing whetherthe input video signal is a telecine signal or not; a frame speeddetection circuit for detecting frame speed of the input video signal todetect whether the detected speed is equal to the frame speed oftelecine video signal; and an AND circuit which obtains the output fromsaid video signal discriminating circuit by calculating the logicalproduct of the discrimination signal and the output from said framespeed detection circuit.
 11. The scan conversion apparatus of claim 10,wherein said frame speed detection circuit comprises: a first weightedsum circuit group for doing the weighted sum between pixels verticallyaligned in the field of the input video signal; a second selector forselecting one of outputs from the first weight sum circuit group; afield memory for delaying the input signal by one field; a secondweighted sum circuit group for doing the weighted sum between pixelsvertically aligned in a field output from said field memory; a thirdselector for selecting one of outputs from said second weighted sumcircuit group; a field detection circuit for detecting kind of the fieldof the input video signal to control said second selector and said thirdselector in accordance with the kind of the field; a first differencecalculator for calculating difference between output from said secondselector and output from said third selector; a frame memory fordelaying the input video signal by one frame; a second differencecalculator for calculating difference between the input video signal andthe output from said frame memory; and a third AND circuit which outputsthe frame speed by obtaining the logical product of output from saidfirst difference calculator and output from said second differencecalculator.
 12. The scan conversion apparatus of claim 10, wherein saidscan conversion circuit generates a progressive scan video signal withuse of said input video signal and highly correlated video signals infields before and after the signal.
 13. The scan conversion apparatus ofclaim 10, wherein said scan conversion circuit generates a progressivescan video signal with use of highly correlated video signals in saidinput video signal.